1. Field of the Invention
The invention relates to a circuit and method for adding a Laplace transform zero to a linear integrated circuit, and more particularly to a circuit and method for adding a Laplace transform zero in a switching regulator feedback loop for providing frequency stability.
2. Description of the Related Art
Closed loop negative feedback systems are commonly employed in linear integrated circuits. For instance, switching regulators use a feedback loop to monitor the output voltage in order to provide regulation. To ensure stability in any closed loop system, the Nyquist criterion must be met. The Nyquist criterion states that a closed loop system is stable if the phase shift around the loop is less than 180 degrees at unity gain. Typically, a compensation circuit is added to a feedback loop to modulate the phase shift of the feedback loop to obtain stability.
The frequency response of a linear circuit can be characterized by the presence of xe2x80x9cpolesxe2x80x9d and xe2x80x9czeros.xe2x80x9d A xe2x80x9cpolexe2x80x9d is a mathematical term which signifies the complex frequency at which gain reduction begins. On the other hand, a xe2x80x9czeroxe2x80x9d signifies the complex frequency at which gain increase starts. Poles and zeros on the left half plane of a complex frequency plane or s-plane are considered normal and can be compensated. However, poles and zeros on the right half plane of a complex frequency plane are usually problematic and difficult to manipulate and is not addressed in the present application. Generally, a pole contributes a xe2x88x9290xc2x0 phase shift while a zero contributes a +90xc2x0 phase shift. A pole cancels out the phase shift of a zero for zeros in the left half plane. In designing a closed loop system with compensation, the location of the poles and zeros are manipulated so as to avoid a greater than 180xc2x0 phase shift at unity gain.
In a linear circuit, poles are created by placing a small capacitor on a node with a high dynamic impedance. If the capacitor is placed at a gain stage, the capacitance can be multiplied by the gain of the stage to increase its effectiveness. Each pole has a zero associated with it. That is, at some point, the dynamic resistance of the gain stage will limit the gain loss capable of being achieved by the capacitor. Thus, a zero can be created by placing a resistor in series with the gain reduction capacitor.
A conventional voltage mode switching regulator uses an inductor-capacitor (LC) network at the voltage output terminal for filtering the regulated output voltage to produce a relatively constant DC output voltage. FIG. 1 is a schematic diagram of a conventional switching regulator including a switching regulator controller 10 and an LC circuit 11. Switching regulator controller 10 generates a regulated output voltage VSW at an output terminal 13 which is coupled to LC circuit 11 for providing a filtered output voltage VOUT. The output voltage VOUT is coupled back to controller 10 at a feedback (FB) terminal 15 for forming a feedback control loop. The LC circuit has associated with it two poles, one pole associated with each element. If the feedback control loop is not compensated, LC circuit 11 alone contributes an xe2x88x92180xc2x0 phase shift to the system and loop instability results, causing the output voltage to oscillate. Because virtually every switching regulator uses an LC filter circuit to filter the regulated output voltage, compensation must be provided in the feedback control loop of a switching regulator to compensate for the effect of the two poles introduced by the LC circuit.
A conventional compensation technique in switching regulators involves adding a circuit in series with the feedback loop which produces a Laplace zero. The zero is added to the feedback control loop to cancel out one of the two poles of the LC filter circuit, thus insuring closed loop stability. U.S. Pat. No. 5,382,918 to Yamatake describes using a capacitance multiplying op-amp to provide a large effective capacitance and a resistor in series as the frequency compensation element of a switching regulator. U.S. Pat. No. 5,514,947 to Berg describes a phase lead compensation circuit for providing additional phase to the loop gain of a switching regulator near the unity gain frequency. The phase lead compensation circuit of Berg uses a transconductance amplifier driving a frequency-dependent load, implemented as a band-limited op amp, in the feedback control loop of the switching regulator. These approaches are problematic because they both require a xe2x80x9chigh qualityxe2x80x9d differential amplifier in operation which are significantly large and complex to realize. In practice, differential amplifiers are typically large devices and can be relatively slow. Furthermore, the differential amplifiers tend to sink large amounts of current proportional to speed. The compensation approaches described by Yamatake and Berg are undesirable because the compensation techniques require sacrificing speed for closed loop stability. In addition the op-amp used in the compensation circuit needs to be compensated for stability itself, making the circuit more complex to implement.
FIG. 1 illustrates another approach for providing compensation in a feedback control loop of a switching regulator. Referring to FIG. 1, the output voltage VOUT is coupled to the feedback terminal 15 and further to a voltage divider including resistors R1 and R2. The operation of the feedback control loop in controller 10 is well known in the art. The voltage divider steps down output voltage VOUT and the divided voltage VR is coupled to an error amplifier 20 which compares the divided voltage VR to a reference voltage VRef. Error amplifier 20 generates an error output signal indicative of the difference between voltage VR and reference voltage VRef. The feedback control loop of controller 10 operates to regulate the output voltage VOUT based on the error output of error amplifier 20 so that voltage VR equals voltage VRef.
FIG. 2a is a plot of the loop gain magnitude vs. frequency in log scale for the switching regulator of FIG. 1 without any compensation. The low frequency loop gain is first reduced by a pole associated with error amplifier 20. The gain loss is modified by a zero also associated with the error amplifier. Then, at high frequency, the effect of the double-pole in the LC filter circuit causes a large loss in the loop gain such that the phase shift at unity gain is equal to or greater than 180xc2x0. The feedback control loop of the uncompensated switching regulator of FIG. 1 is unstable unless the gain is substantially reduced.
In the switching regulator of FIG. 1, a capacitor 18 (typically referred to as a xe2x80x9czero capacitorxe2x80x9d) is connected in parallel to resistor R1 of the voltage divider. Capacitor 18 introduces a zero-pole pair in the feedback loop. The location (or frequency) of the zero-pole pair is determined by the resistance of the voltage divider and the capacitance of capacitor 18. For practical resistance and capacitance values, the zero and pole introduced by capacitor 18 are typically located close to each other so that the zero is canceled out quickly by the nearby associated pole. FIG. 2b is a plot of the loop gain magnitude vs. frequency in log scale in the switching regulator of FIG. 1 incorporating zero capacitor 18. Here, the operation of the zero capacitor ensures that the phase shift is less than 180xc2x0 near unity gain. However, the compensation provided by zero capacitor 18 is limited and often does not provide sufficient phase margin at unity gain. For example, at high frequency, zero capacitor 18 shorts out resistor R1, resulting in no or minimal gain loss in the feedback loop. Thus, the compensation provided by capacitor 18 is not effective at high frequency. Also, the voltage divider of resistors R1 and R2 typically provides only a gain loss of 3 dB. The 3 dB gain loss limits the ratio of the pole to zero angular frequency of capacitor 18, and thus, limits the compensation range capable of being achieved by the use of a single zero capacitor 18. The feedback loop of switching regulator of FIG. 1 is susceptible to instability when the switching regulator is subjected to fluctuations in load impedance because of this limited compensation range.
Thus, it is desirable to provide a compensation circuit in a feedback loop of a linear circuit which is capable of providing effective pole cancellation.
According to one aspect of the present invention, a switching regulator controller circuit includes an output terminal providing a signal corresponding to a regulated output voltage and a feedback terminal for receiving a first voltage corresponding to the regulated output voltage. The controller circuit further includes an error amplifier having a first input node coupled to receive a feedback voltage corresponding to the first voltage, a second input node coupled to a reference voltage, and an error output node providing an error voltage indicative of the difference between the feedback voltage and the reference voltage. The controller circuit also includes a control circuit including an input node receiving the error voltage and an output node generating the signal corresponding to the regulated output voltage in response to the error voltage, the control circuit coupling the signal to the output terminal.
The controller circuit includes a compensation circuit for introducing a zero in the circuit for frequency stabilization. The compensation circuit includes a first capacitor coupled between the first input node of the error amplifier and a first node where the first capacitor blocks out the DC component of the feedback voltage, an amplifier coupled between the first node and a second node, and a second capacitor coupled between the second node and the first input node of the error amplifier. The compensation circuit introduces a zero at the first input node of the error amplifier.
In another embodiment, the second capacitor of the compensation circuit is coupled between the second node and a third node coupled to a summing circuit. The compensation circuit introduces a zero at a summing node of the summing circuit for summing a voltage corresponding to the zero and the error voltage of the error amplifier.
In yet another embodiment, the error amplifier includes a first gain stage, a summing circuit and a second gain stage. The second capacitor of the compensation circuit is coupled between the second node and a summing node coupled to the summing circuit of the error amplifier. The compensation circuit thus introduces a zero at the summing node of the error amplifier.
According to another aspect of the present invention, a compensation circuit for introducing a zero in a first circuit being incorporated in a closed loop feedback system is provided. The first circuit includes a first terminal generating a first voltage for the closed loop feedback system and a feedback terminal for receiving a second voltage from the closed loop feedback system. The first circuit also includes an input node receiving a feedback voltage corresponding to the second voltage where the input node is coupled to an error amplifier.
The compensation circuit includes a first capacitor coupled between the input node in the first circuit and a first node where the first capacitor blocks out the DC component of the feedback voltage, an amplifier coupled between the first node and a second node, and a second capacitor coupled between the second node and a summing node in the error amplifier. The summing node is coupled to a summing circuit disposed between a first gain stage and a second gain stage of the error amplifier in the first circuit.
The compensation circuit amplifies the capacitance of the second capacitor and introduces a zero in the first circuit effective for pole-cancellation in the closed loop feedback system. Furthermore, the zero introduced by the compensation circuit has effectiveness over a wide range of frequencies.